View M48Z512A_143795.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M48Z512A M48Z512AY
4 Mbit (512Kb x8) ZEROPOWER(R) SRAM
s
INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z512A: 4.50V VPFD 4.75V - M48Z512AY: 4.20V VPFD 4.50V
32
32 1
s
s
s
PMDIP32 (PM) Module SNAPHAT (SH) Battery
s
s
BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 512K x 8 SRAMs SURFACE MOUNT CHIP SET PACKAGING INCLUDES a 28-PIN SOIC and a 32-LEAD TSOP (SNAPHAT TOP TO BE ORDERED SEPARATELY) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP WHICH CONTAINS the BATTERY SNAPHAT(R) HOUSING (BATTERY) IS REPLACEABLE
19
1
s
TSOP II 32 (10 x 20mm) SOH28 Surface Mount Chip Set Solution (CS)
s
s
Figure 1. Logic Diagram
s
VCC
8 DQ0-DQ7 M48Z512A M48Z512AY
Table 1. Signal Names
A0-A18 DQ0-DQ7 E G W VCC VSS March 2000 Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground
A0-A18
W E G
VSS
AI02043
1/17
M48Z512A, M48Z512AY
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TBIAS TSLD (2) V IO VCC Parameter Ambient Operating Temperature Storage Temperature (V CC Off) Temperature Under Bias Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Value 0 to 70 -40 to 70 -40 to 70 260 -0.3 to 7 -0.3 to 7 Unit C C C C V V
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode Deselect Write Read Read Deselect Deselect VSO to VPFD (min) VSO 4.75V to 5.5V or 4.5V to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z D IN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Figure 2. DIP Connections
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 M48Z512A 25 9 M48Z512AY 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17
AI02044
VCC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
DESCRIPTION The M48Z512A/512AY ZEROPOWER(R) RAM is a non-volatile 4,194,304 bit Static RAM organized as 524,288 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32 pin DIP Module. For surface mount environments ST provides a Chip Set solution consisting of a 28 pin 330mil SOIC NVRAM Supervisor (M40Z300) and a 32 pin TSOP Type II (10 x 20mm) LPSRAM (M68Z512) packages. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is "M4Zxx-BR00SH1".
2/17
M48Z512A, M48Z512AY
Figure 3. Block Diagram
VCC
A0-A18
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
512K x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERY
VSS
AI02045
The M48Z512A/512AY also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns. The ZEROPOWER RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs without any requirement for special write
timing or limitations on the number of writes that can be performed. The M48Z512A/512AY has its own Power-fail Detect Circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operations brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which sustains data until valid power returns.
3/17
M48Z512A, M48Z512AY
Figure 4. Hardware Hookup for SMT Chip Set (1)
THS(2) SNAPHAT BATTERY(3)
VOUT
VCC E2
M40Z300 E E1CON E2CON E3CON E4CON A RST B BL VSS W E
M68Z512 DQ0-DQ7
A0-A18
VSS
AI03631
Note: 1. For pin connections, see individual data sheets for M40Z300 and M68Z512 at www.st.com. 2. Connect THS pin to VOUT if 4.2V VPFD 4.5V (M48Z512AY) or connect THS pin to VSS if 4.5V VPFD 4.75V (M48Z512A). 3. SNAPHAT top ordered separately.
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Figure 5. AC Testing Load Circuit
5V
Note that Output Hi-Z is defined as the point where data is no longer driven.
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
AI01030
4/17
M48Z512A, M48Z512AY
Table 5. Capacitance (1, 2) (TA = 25 C, f = 1MHz)
Symbol C IN CIO (3) Parameter Input Capacitance Input / Output Capacitance Test Condit ion VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected.
Table 6. DC Characteristics (TA = 0 to 70 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI (1) ILO (1) ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 Test Conditio n 0V VIN VCC 0V VOUT VCC E = VIL, Outputs open E = VIH E VCC - 0.2V -0.3 2.2 Min Max 1 1 115 10 5 0.8 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
Note: 1. Outputs deselected.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 C)
Symbol VPFD V SO tDR (2) Parameter M48Z512A Power-fail Deselect Voltage M48Z512AY Battery Back-up Switchover Voltage Data Retention Time 10 4.2 4.3 3 4.5 V V YEARS Min 4.5 Typ 4.6 Max 4.75 Unit V
Note: 1. All voltages referenced to VSS. 2. At 25 C.
5/17
M48Z512A, M48Z512AY
Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 C)
Symbol tF (1) tFB (2) tWP tR tER Parameter V PFD (max) to VPFD (min) VCC Fall Time V PFD (min) to VSO VCC Fall Time Write Protect Time from VCC = VPFD V SO to VPFD (max) VCC Rise Time E Recovery Time Min 300 10 40 0 40 120 150 Max Unit s s s s ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 6. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWP E
RECOGNIZED
tDR
tR
tER DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
6/17
M48Z512A, M48Z512AY
Table 9. Read Mode AC Characteristics (TA = 0 to 70 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z512A/M48Z512AY Symbol Parameter Min tAVAV tAVQV (1) tELQV (1) tGLQV (1) tELQX (2) tGLQX (2) tEHQZ (2) tGHQZ (2) tAXQX (1) Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 5 5 5 30 20 5 70 70 70 35 5 5 35 25 -70 Max Min 85 85 85 45 -85 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 100pF. 2. CL = 5pF.
Figure 7. Address Controlled, Read Mode AC Waveforms
A0-A18 tAVAV tAVQV DQ0-DQ7 DATA VALID
AI01220
tAXQX
Note:
Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
7/17
M48Z512A, M48Z512AY
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV A0-A18 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI01221
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
READ MODE The M48Z512A/512AY is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripplethrough access of data from eight of 4,194,304 locations in the static storage array. Thus, the unique address specified by the 19 Address Inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E (Chip Enable) and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be
available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
8/17
M48Z512A, M48Z512AY
Table 10. Write Mode AC Characteristics (TA = 0 to 70 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z512A/M48Z512AY Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1, 2) tAVWH tAVEH tWHQX (1, 2) Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 65 65 5 70 0 0 55 55 5 15 30 30 0 10 25 75 75 5 -70 Max Min 85 0 0 65 75 5 15 35 35 0 10 30 -85 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 5pF. 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE MODE The M48Z512A/512AY is in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tE-
from E or tWHAX from W prior to the initiation of another read or write cycle. Data-in must be valid t DVEH or tDVWH prior to the end of write and remain valid for tEHDX or tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
HAX
9/17
M48Z512A, M48Z512AY
Figure 9. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01222
tWHAX
tWHQX
Note: Output Enable (G) = High.
Figure 10. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01223
tELEH
tEHAX
Note: Output Enable (G) = High.
10/17
M48Z512A, M48Z512AY
Figure 11. Supply Voltage Protection The internal coin cell will maintain data in the M48Z512A/512AY after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO , the battery is disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on Battery Storage Life refer to the Application Note AN1012. POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 11) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommeded to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
VCC VCC
0.1F
DEVICE
VSS
AI02169
DATA RETENTION MODE With valid VCC applied, the M48Z512A/512AY operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data.
11/17
M48Z512A, M48Z512AY
Table 11. Ordering Information Scheme
Example: Device Type M48Z Supply Voltage and Write Protect Voltage 512A = VCC = 4.75V to 5.5V; VPFD = 4.5V to 4.75V 512AY = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V Speed -70 = 70ns -85 = 85ns Package PM = PMDIP32 CS (1) = Surface Mount Chip Set solution M40Z300 (SOH28) + M68Z512 (TSOP II 32) Temperature Range 1 = 0 to 70 C 9 (2) = Extended Temperature M48Z512AY -85 PM 1
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT ) which is ordered separately under the part number "M4Zxx-BR00SH1" in plastic tube or "M4Zxx-BR00SH1TR" in Tape & Reel form. 2. Contact Sales Offices for availability of Extended Temperature. Caution: Do not place the SNAPHAT battery package "M4Zxx-BR00SH1" in conductive foam since this will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
12/17
M48Z512A, M48Z512AY
Table 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data
mm Symbol Typ A A1 A2 b C CP D e E E1 L N 1.27 20.82 - 11.56 10.03 0.40 0 32 0.05 0.95 0.30 0.12 Min Max 1.20 0.15 1.05 0.52 0.21 0.10 21.08 - 11.96 10.29 0.60 5 0.050 0.820 - 0.455 0.395 0.016 0 32 0.002 0.037 0.012 0.005 Typ Min Max 0.047 0.006 0.041 0.020 0.008 0.004 0.830 - 0.471 0.405 0.024 5 inches
Figure 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline
D
16
1
E1
E
17
32
b
e
A
A2 C A1 CP L
TSOP-d
Drawing is not to scale. 13/17
M48Z512A, M48Z512AY
Table 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
Figure 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Drawing is not to scale.
14/17
M48Z512A, M48Z512AY
Table 14. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data
mm Symbol Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090 inches
Figure 14. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Drawing is not to scale.
15/17
M48Z512A, M48Z512AY
Table 15. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm Symbol Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 34.29 14.99 3.05 1.91 32 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 41.91 16.00 3.81 2.79 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.350 0.590 0.120 0.075 32 Max 0.375 - 0.023 0.013 1.700 0.740 0.110 1.650 0.630 0.150 0.110 inches
Figure 15. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Drawing is not to scale.
16/17
M48Z512A, M48Z512AY
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com
17/17

▲Up To Search▲

Price & Availability of M48Z512A

	To Download M48Z512A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .